The present invention is directed to analog-to-digital converter apparatuses, and especially to a method for improving linearity of performance for an analog-to-digital converter apparatus.
The so-called “pipelined” architectures for Analog-to-Digital Conversion (ADC) rely on the concept of simultaneous data sub-conversion in multiple stages in order to progressively refine the digital representation of an analog signal. There are two fundamental approaches to pipelined ADC: switched-capacitor and switched-current. In both of these approaches, ADC apparatuses are impacted by the matching of components employed in the local quantization path of each stage.
Switched-current designs will suffer from mismatches between the elements of the folding sub-ADC, and from mismatches among the current source elements constituting the reconstruction DAC (Digital-to-Analog Converter). The DAC could be segmented in different ways to vary the impact of the mismatch. However, once the mismatch between the elementary DAC elements has been minimized, the relative current mismatch between first ADC stage and the second ADC stage (and between later stage-pairs) will remain to be addressed.
In switched-capacitor ADC implementations the relative size of the capacitors determines the gain of the stage and also determines the size of the voltage steps in the reconstruction MDAC (Multiplying Digital-to-Analog Converter), directly impacting the integral non-linearity (INL). These technology-related mismatches have become increasingly critical in the latest releases of minimum-feature CMOS (Complementary Metal Oxide Semiconductor) and BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) processes, because the lithographic control over both active and passive devices is more difficult to attain. This technological problem is expected to be exacerbated in the future. The answer by the design community to this challenge led to develop at least two classes of techniques which employ analog rather than digital solutions in order to correct for these mismatches.
All-digital bit-redundancy techniques have proven effective to tackle the sub-ADC imperfections. The sub-DAC non-idealities have been addressed using digital calibration methods (e.g., one-time adjustments or continuous background calibration) or using analog “trimming” of devices impacted by a statistical mismatch.
Non-brute-force trimming techniques depend upon a preliminary identification of the errors affecting the INL (Integral Non-Linearity; measure of departure from the ideal linear transfer curve for an ADC) such as positive or negative gaps. Once the errors have been assessed, the passive components that determine such an ADC behavior can be adjusted to compensate for their non-ideality. For example, selective laser cuts can trim the value of resistors in a DAC to linearize the analog signal translation from the digital word. Alternatively, tiny parasitic capacitors can be switched in parallel to the signal capacitors of a quantizer's stages to counter a process-induced mismatch.
Unless time-consuming, computer processing-consuming and memory-consuming brute force or iterative approaches are followed, the algorithms used to configure the trim circuitry for reducing component mismatches must have available a reliable identification of the INL errors in order to work. For example, in the case of a 16-bit switched-capacitor pipeline ADC, trying out all the different combinations of the trim values, collecting INL or SFDR (Spurious Free Dynamic Range; difference between the Root Mean Square (RMS) value of a desired output signal and the highest amplitude output frequency that is not present in the input) measurements in every instance and finding the best trim code is not a reasonable approach. If every trim device controlled one and one only error the optimization problems would be completely decoupled, and they could be solved with minimal effort. Indeed, especially in the switched-capacitor paradigm where a feedback capacitor controls the gain of the stage and therefore affects mismatches and trimming for a plurality of other components, the passive component change that fixes one mismatch could make other errors or mismatches worse. To properly arrive at a solution, the solutions to every mismatch of an apparatus are coupled and must be found considering all the mismatch errors simultaneously. Unfortunately, for example, a simple 4 bits accurate trim over a 2.5 bit per stage quantizer (4 capacitors (caps) for each stage) produces a string of 4 bits×4 caps=16 bit-long trim word, for a total of 216=65,536 permutations for each stage. The simultaneous trimming of the first 2 stages of such a pipeline requires as many as 232=4,294,967,296 attempts. Each attempt involves a trim programming and re-measurement process with possible follow-up retrimming and measurement steps. Such an approach is therefore impracticable for most if not all the high-resolution systems available to date.
There is a need for a method for improving linearity of an analog-to-digital converter (ADC) that employs other than brute force to solve mismatch problems.
There is a need for a method for improving linearity of an analog-to-digital converter (ADC) that is non-iterative in that no repetitive trim-and-measure operations are required for its implementation.